The present invention relates to a semiconductor memory device, and more particularly to a switching between burst mode and normal mode of the semiconductor memory device.
The majority of the advanced dynamic random access memory is a synchronous dynamic random access memory (SDRAM) which is operable in high speed clock such as 100 MHz. This SDRAM may be fabricated in almost the same cost as the conventional DRAM. The SDARM is operated in burst mode which allows sequential or continuous accesses to memory cells in the same page upon once input of the address. For example, in the burst mode, one of plural modes is selected, so as to allow continuous and sequential accesses to 1, 2, 4 and 8 bits data or all bits data on one page.
In order to discontinue the operation in the burst mode of the SDRAM, it is necessary to enter a burst stop command or a pre-charge command.
In order to realize a highly efficient data transmission between the SDRAM and the CPU or controller, it is highly required to reduce the number of the commands or instructions. Particularly, the burst stop command may be substituted by the pre-charge command. The CPU or controller may be free of the burst stop command. Namely, in the SDRAM, two systems co-exist wherein the first type system has the burst stop command whilst the second type system is free from the burst stop command and the second system.
If the burst stop command is eliminated from the system using the SDRAM, only the pre-charge command is the sole commend to stop the operation of the SDRAM in the burst mode. No particular problem is raised in the system using the normal SDRAM.
By the way, the present inventor had proposed a virtual channel synchronous dynamic random access memory (VCSDRAM) or increase the access speed. The virtual channel memory a memory cell array of plural DRAM memory cells aligned in matrix, and a resistor array having row and column numbers in correspondence with the row and column numbers of the memory cell array and having a cache function. The resistor array comprises SRAM.
The above virtual channel memory combines SRAM and DRAM is incapable of ending the read and write operations in the burst mode as a foreground operation from the resistor array with the pre-charge command as the background operation.
In the system free of the burst stop command, it is difficult to discontinue the operation in the burst mode of the virtual channel memory for change to the normal operation mode.
In the above circumstances, it had been required to develop a novel semiconductor memory device free from the above problem.